IBIS Macromodel Task Group

Meeting date: 16 Jan 2007

Members (asterisk for those attending):
* Arpad Muranyi, Intel Corp.
  Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
* Doug White, Cisco Systems
* Hemant Shah, Cadence Design Systems
  Ian Dodd, Mentor Graphics
  Joe Abler, IBM
* John Angulo
  John Shields, Mentor Graphics
  Ken Willis, Cadence Design Systems
* Kumar, Cadence Design Systems
* Lance Wang, Cadence Design Systems
  Luis Boluna, Cisco
* Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
* Patrick O'Halloran, Tiburon Design Automation
  Paul Fernando, NCSU
* Randy Wolff, Micron Technology
* Richard Ward, Texas Instruments
  Sanjeev Gupta, Agilent
  Shangli Wu, Cadence
* Syed Huq, Cisco Systems
  Todd Westerhoff, SiSoft
* Walter Katz, SiSoft
  Vuk Borich, Agilent
  Vikas Gupta, Xilinx

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Review of ARs:

- Mike: update macro library documentation
  Was waiting for version confirmation, now received.

- Mike post minutes to web site
  Done

- Arpad write parameter passing syntax proposal
  TBD

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New Discussion:

Should we post the Mentor SPICE-equivalent VHDL elements?
- Part of SystemVision download
- Need to be clear that it does not correspond to our macro library.
- Could put it in the archive area only.
- No decision this week.

Special meeting at DesignCon
- Extend the IBIS summit?
  - We have the room until 5:00 PM
- Might want 2-2.5 hours
- If we meet at Mentor we might have logistics problems
- People will be travelling Thursday.
- Right after the summit would be best.
  - Schedule currently runs to about 3:00 PM
  - We will use the summit room
  - Not sure what to do about food

AR: Michael Mirmak try to reserve room until 7:00 PM
AR: Todd to update DesignCon IBIS Summit Presentation, add HSpice resolution to it

IBIS Summit presentation
- No new progress to report

API discussion
- Cadence has a few minor changes to their proposal.
- Cadence prefers DLL over .EXE format
  - Hemant: DLL should be fast and more flexible
  - Barry: but DLL raises portability issues
  - Todd: will only be executed once, right? What is the performance problem?
  - Arpad: Ian had proposed non-compiled (source) delivery
    - No one liked that
    - Mirmak: compiling Verilog-A was a pain
- Todd: no one is designing a TX that needs an API
  - Richard: may need API for duty cycle distortion handling
    - can use HSPICE or AMS
    - Need to be able to introduce jitter into the TX
    - Let's use simple TX, work on RX processing, and propose extensions
      later to enhance TX
  - Todd: EQ in TX is not the same as in RX
  - Mirmak: need to support tool side waveform processing beyond what the
    buffer does; this needs a capable API
  - Kumar: no need to artifically restrict TX or RX
  - Walter: 3 issues
    1 - min TX requirement is parameters
      - characterization, # taps, jitter, etc.
    2 - When you use this TX, here is the way to optimize
    3 - ?
- Mirmak: want some place to stick algorithmic, non-silicon code
  - IC vendors are coding tools instead of waiting for EDA vendors.
  - Need this yesterday
  - Example: worst-case eye analysis
- Todd: need an agreed standard on model inputs and outputs
- Todd: Can we really pump enough bits to predict bit error rate?
  - Richard: need at least 1 million bits
    - Todd: maybe more
- Todd: GetWave() is primarily time based
  - Kumar: may not always need GetWave()

AR: Todd have presentation for review by next meeting

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Next meeting: Tuesday 23 Jan 2006 12:00pm PT